After synthesizing your netlist, load it into memory with the XDC files or Tcl scripts enabled for implementation. Review messages when loading the XDC to verify and correct unapplied constraints. If synthesized netlist names differ, recreate constraints and save them in an implementation-only XDC file.
After all XDC files load properly, run timing analysis to:
- Add missing constraints, such as input and output delay.
- Add timing exceptions, such as false paths, multicycle paths, and min/max delay constraints.
- Identify and correct large violations caused by long paths in the design by updating the RTL description.
You can reuse the same base constraints from synthesis and create a second XDC file for new constraints specific to implementation. You can also save physical and configuration constraints in a separate XDC file.
Note: In project mode, opening a
synthesized design links the post-synthesis DCP netlist(s) to build the full top-level
hierarchical netlist. All XDC constraints marked for implementation load automatically,
enabling verification on the full synthesized design. If you modify implementation
constraints, the opened synthesized design becomes out of date (not the synthesized
run). Vivado IDE displays a banner and provides an option
to reload the design.
Figure 1 shows the netlist-based XDC iteration.