Creating Implementation Constraints - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

After you have a synthesized netlist, you can load it into memory together with the XDC files or Tcl scripts enabled for implementation. You must review the messages issued by the tool when loading the XDC to verify and correct any constraint that cannot be applied.

In some cases, the object names in the synthesized netlist are different from the names in the elaborated design. If this is the case, you must recreate some constraints with the corrected names, and save them in an implementation-only XDC file.

After the tool can properly load all the XDC files, you can run timing analysis to:

  • Add missing constraints, such as input and output delay.
  • Add timing exceptions, such as false paths, multicycle paths, and min/max delay constraints.
  • Identify large violations due to long paths in the design and correct the RTL description.

You can use the same base constraints as used during synthesis, and create a second XDC file to store all new constraints specific to implementation. You can choose to save physical and configuration constraints in a separate XDC file.

Note: In project mode, opening a synthesized design results in linking the netlist(s) from the post-synthesis DCP(s) to build the full top-level hierarchical netlist. All XDC constraints marked for implementation are also automatically loaded. This enables you to verify the implementation constraints on the full synthesized design. This means that if the implementation constraints are modified, the opened synthesized design goes out of date, not the synthesized run. The GUI shows a small banner and provides the option to reload the design.

The netlist-based XDC iteration is shown in Figure 1.