Do not use set_max_delay or set_min_delay for input or
output logic on a regular basis. Constrain logic between input ports and the first
register stage with set_input_delay, which lets you associate a clock
with the input ports.
For outputs, constrain logic between the last register stage and the output ports with
set_output_delay. Use set_max_delay or
set_min_delay for pure combinational in-to-out I/O paths between
primary inputs and primary outputs.