Constraining Asynchronous Signals - Constraining Asynchronous Signals - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

Use set_max_delay to constrain asynchronous signals that lack a clock relationship but require a maximum delay. For example, disable timing between asynchronous clock domains with set_clock_groups (recommended) or set_false_path (not recommended), assuming proper CDC design like double-register synchronizers or FIFOs. Continue to keep path delays between the domains within a reasonable bound.

In multi-bit CDCs, limit bit-to-bit skew. Even if you constrain skew with set_bus_skew, also bound the path delay between domains. Replace set_false_path or set_clock_groups on the relevant paths in the source XDC with:
set_max_delay -datapath_only <delay> -from <startpoints> -to <endpoints>

Refer to CDC Constraints for CDC guidance.

Note: A max delay constraint impacts runtime compared to a false path because the tool times those paths.

If you need a maximum delay on some or all paths between two clock domains, use set_max_delay -datapath_only on those paths. Do not use set_clock_groups to mark the domains asynchronous in that case, because it overrides set_max_delay by priority. Constrain remaining cross-domain paths with set_false_path and/or additional set_max_delay constraints.

Example:
set_max_delay <delay> -datapath_only \
-from <startpoints_source_clock_domain> \
-to <endpoints_destination_clock_domain>