Combinational Delays - Combinational Delays - 2026.1 English - UG903

Some paths propagate directly from input ports to output ports without being captured by a sequential cell. Follow these steps for combinational path delay constraints:

1. Check connectivity.
   • If an input port connects to both an output port and a sequential cell, do not use combinational constraints.
   • Instead, define a virtual clock with input and output delays.
   
   
   
2. Define combinational delay constraints.
   • For setup analysis: virtual clock period – max input delay – max output delay
   • For hold analysis: 0 – min output delay – min input delay
3. Adjust the virtual clock period.
   • Ensure it is greater than the largest combinational delay across all constrained paths.
   • The figure shows the delay entries needed for each input/output pair.
   
   
   
4. Review delay constraints.
   • None of the input or output delay constraints override existing ones.
   • If a port has multiple delay constraints for the same clock, Vivado timing analysis uses:
     • The smallest value for hold analysis
     • The largest value for setup analysis
5. After filling all delay entries, click Next to proceed to the next step.