Clock Latency - Clock Latency - 2026.1 English - UG903

As the clock propagates on the board and inside the FPGA, edges arrive with delay. You can represent this delay using the following latency types:

• Source latency (delay before the clock source point, usually, outside the device)
• Network latency

Pre-route, the tool estimates insertion delay. Post-route, it computes insertion delay accurately.

Many non-AMD timing engines require the SDC command set_propagated_clock to trigger propagation-delay computation along clock trees. Vivado does not require this and computes clock propagation delay by default:

• Treat all clocks as propagated clocks.
• A generated clock’s latency includes the master clock insertion delay plus its own network latency.

For AMD FPGAs, use set_clock_latency primarily to specify clock latency outside the device.

# Minimum source latency value for clock sysClk (for both Slow and Fast corners) 
set_clock_latency -source -early 0.2 [get_clocks sysClk]

# Maximum source latency value for clock sysClk (for both Slow and Fast corners) 
set_clock_latency -source -late 0.5 [get_clocks sysClk]