Clock Jitter - Clock Jitter - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document_ID
UG903
Release_Date
2026-07-01
Version
2026.1 English

For ASIC devices, you represent clock jitter with clock uncertainty. For AMD FPGAs, jitter properties are predictable. You can let the timing engine compute them automatically, or specify them separately.