Clock Jitter - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

For ASIC devices, clock jitter is usually represented with the clock uncertainty characteristic. However, for AMD FPGAs, the jitter properties are predictable. They can be automatically computed by the timing analysis engine, or be specified separately.