In some designs, certain signals maintain a constant value in specific modes. For example, in functional modes, test signals do not toggle and are tied to either VDD or VSS depending on their active level. The same applies to signals that stop toggling after power-up. In modern designs with multiple functional modes, signals that are active in one mode can be inactive in another.
To help reduce analysis space, runtime, and memory consumption, it is important to inform the Static Timing Engine about signals that hold a constant value. This also prevents non-functional and irrelevant paths from being reported.
Use the set_case_analysis command to
declare a signal as inactive to the timing engine. This command applies to pins or
ports.
set_case_analysis <value> <pins or ports objects>1 on a non-inverted pin is equivalent to a value of 0 on a pin with IS_INVERTED equal to 1. Vivado does not automatically adjust the case value based
on inversion. It is your responsibility to specify the correct value. If the pin is
inverted after applying the constraint, you must also update the case value
accordingly.set_case_analysis, refer to
Vivado Design Suite QuickTake Video: Advanced
Timing Exceptions - False Path, Min-Max Delay and Set_Case_Analysis.The parameter <value> can be any of the following: 0, 1, zero, one, rise, rising, fall, or falling.
When using rise, rising, fall, or falling, the specified pins or ports are included in timing analysis only
for the given transition. The other transition is disabled.
You can apply case values to ports, pins of leaf cells, or pins of hierarchical modules.
In the following example, two clocks are created on the input pins of a
multiplexer clock_sel. After setting a constant value
on the selection pin S, only clk_2 propagates through the output:
create_clock -name clk_1 -period 10.0 [get_pins clock_sel/I0]
create_clock -name clk_2 -period 15.0 [get_pins clock_sel/I1]
set_case_analysis 1 [get_pins clock_sel/S]In the following example, the BUFG_GT
has dynamic clock division, with its DIV[2:0] pins
driven by logic instead of being tied to VCC or GND.
In this case, BUFG_GT has dynamic
division control through the DIV[2:0] pins. These pins
are driven by logic instead of being tied to VCC or
GND. By default, the tool assumes the worst case
scenario (divide by 1) and propagates the incoming clock directly to the output. This
can over-constrain the design if divide by 1 is never used.
To control the auto-generated clock on the BUFG_GT output pin, apply case analysis to the DIV bus. For example, to model a divide by 3 configuration:
set_case_analysis 0 [get_pins bufg_gt_pclk/DIV[0] ]
set_case_analysis 1 [get_pins bufg_gt_pclk/DIV[1] ]
set_case_analysis 0 [get_pins bufg_gt_pclk/DIV[2] ]GT_CHANNEL contains multiple input clocks that propagate to outputs like
TXOUTCLK through internal multiplexers. Use case
analysis in the same way on control signals such as TXSYSCLKSEL or TXOUTCLKSEL to specify
which internal or external clock propagates to the output.BUFGCTRL Example
S0 and S1:set_case_analysis 0 [get_pins <BUFGCTRL/S0>]
set_case_analysis 1 [get_pins <BUFGCTRL/S1>]The input pin S0 is driven by an
inverter:
BUFGCTRL/S0 during optimization, the case analysis value must be
updated by the user to reflect the inversion on pin S0:set_case_analysis 0 [get_pins <BUFGCTRL/S0>]