CLOCK_DEDICATED_ROUTE - CLOCK_DEDICATED_ROUTE - 2026.1 English - UG903

Use the CLOCK_DEDICATED_ROUTE property on a clock net to specify how the clock signal routes. This property overrides the default clock routing and is considered an advanced setting. Apply it with extreme caution, as it can impact both timing predictability and routability.

For example, you can set CLOCK_DEDICATED_ROUTE to FALSE when dedicated clock routing resources are unavailable. This lets Vivado route the clock from an input port to a global clocking resource (like BUFG or MMCM) using general routing. Use this only as a last resort when package pin assignments are fixed and the clock input cannot connect to a dedicated clock‑capable input (CCIO).

The resulting routing is suboptimal and can be unpredictable unless combined with FIXED_ROUTE.

For more details, refer to the Clock Constraints section in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).