Set the ASYNC_REG property to true on all synchronizer
flip-flops. This preserves the synchronizer cells through synthesis and implementation
optimization and improves placement for better mean time between failures (MTBF)
statistics.
For any clock group constraints enabled in either table, the wizard sets missing
ASYNC_REG properties to true. For details on the ASYNC_REG
property, refer to
Vivado
Design Suite Properties Reference Guide (UG912).