AMD recommends that all synchronizer flip-flops have their ASYNC_REG property set to true to preserve the synchronizer cells through any logic optimization during synthesis and implementation, and to optimize their placement for best Mean Time Between Failures (MTBF) statistics. For any clock group constraints that are enabled in both tables (either by default or by the user), the wizard sets to true any missing ASYNC_REG property.
Refer to the
Vivado
Design Suite Properties Reference Guide (UG912) for detailed information about the
ASYNC_REG property.