BEL/LOC Constraints - BEL/LOC Constraints - 2026.1 English - UG903

For complex structures, specify the BEL or LOC constraints in addition to the RLOC when needed. Use the BEL constraint to align cells inside the RPM set, for example, to align LUTs with registers. The LOC constraint is uncommon and rarely used because it forces the RPM set onto a specific device site, preventing the placer from moving it.

When specifying BEL or LOC constraints, do not mix their sources. Define all BEL and LOC constraints either in RTL or in XDC, not in both.

Here is an example of BEL constraints specified in RTL using a Verilog file:

(*BEL="H6LUT",RLOC="X0Y0"*) LUT6 S0_LUTH (...); 
(*BEL="G6LUT",RLOC="X0Y0"*) LUT6 S0_LUTG (...); 
(*BEL="F6LUT",RLOC="X0Y0"*) LUT4 S0_LUTF (...); 
(*BEL="E5LUT",RLOC="X0Y0"*) LUT4 S0_LUTE (...); 
(*BEL="D6LUT",RLOC="X0Y0"*) LUT6 S0_LUTD (...); 
(*BEL="C6LUT",RLOC="X0Y0"*) LUT6 S0_LUTC (...); 
(*BEL="B6LUT",RLOC="X0Y0"*) LUT4 S0_LUTB (...); 
(*BEL="A5LUT",RLOC="X0Y0"*) LUT4 S0_LUTA (...);

(*BEL="CARRY8",RLOC="X0Y0"*) CARRY8#(.CARRY_TYPE("DUAL_CY4")) S0_CARRY8(...);
 
(*BEL="HFF2",RLOC="X0Y0"*) FD FD_out5 (...);
(*BEL="GFF2",RLOC="X0Y0"*) FD FD_out4 (...);
(*BEL="FFF2",RLOC="X0Y0"*) FD FD_out3 (...);
(*BEL="DFF2",RLOC="X0Y0"*) FD FD_out2 (...);
(*BEL="CFF2",RLOC="X0Y0"*) FD FD_out1 (...);
(*BEL="BFF2",RLOC="X0Y0"*) FD FD_out0 (...);

In the following examples, the RPM is defined in RTL, and the BEL constraints are specified through XDC.

(*RLOC="X0Y0"*) LUT6 S0_LUTH (...);
(*RLOC="X0Y0"*) LUT6 S0_LUTG (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTF (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTE (...);
(*RLOC="X0Y0"*) LUT6 S0_LUTD (...);
(*RLOC="X0Y0"*) LUT6 S0_LUTC (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTB (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTA (...);

(*RLOC="X0Y0"*) CARRY8#(.CARRY_TYPE("DUAL_CY4")) S0_CARRY8(...);
 
(*RLOC="X0Y0"*) FD FD_out5 (...);
(*RLOC="X0Y0"*) FD FD_out4 (...);
(*RLOC="X0Y0"*) FD FD_out3 (...);
(*RLOC="X0Y0"*) FD FD_out2 (...);
(*RLOC="X0Y0"*) FD FD_out1 (...);
(*RLOC="X0Y0"*) FD FD_out0 (...);

set_property BEL CARRY8 [get_cells S0_CARRY8] 
set_property BEL HFF2 [get_cells FD_out5] 
set_property BEL GFF2 [get_cells FD_out4] 
set_property BEL FFF2 [get_cells FD_out3] 
set_property BEL DFF2 [get_cells FD_out2] 
set_property BEL CFF2 [get_cells FD_out1] 
set_property BEL BFF2 [get_cells FD_out0] 
set_property BEL A5LUT [get_cells S0_LUTA] 
set_property BEL B6LUT [get_cells S0_LUTB] 
set_property BEL C6LUT [get_cells S0_LUTC] 
set_property BEL D6LUT [get_cells S0_LUTD] 
set_property BEL E5LUT [get_cells S0_LUTE]
set_property BEL F6LUT [get_cells S0_LUTF] 
set_property BEL G6LUT [get_cells S0_LUTG] 
set_property BEL H6LUT [get_cells S0_LUTH]