Automatically derived clocks are also called auto-generated clocks. Vivado IDE automatically creates constraints for these clocks on output pins of CMBs after you define the associated master clock.
In the AMD 7 series device family, the CMBs are as follows:
- MMCM*/ PLL*
- BUFR
- PHASER*
In the UltraScale, UltraScale+, and Versal device families, the CMBs are as follows:
- MMCM* / PLL*
- BUFG_GT / BUFGCE_DIV
- GT*_COMMON / GT*_CHANNEL / IBUFDS_GTE*
- BITSLICE_CONTROL / RX*_BITSLICE
- ISERDESE*
Vivado does not create an auto-generated clock if you manually define a primary or generated clock on the same netlist object (net or pin). Vivado names the auto-derived clock after the segment name at the top-most hierarchy of the net connected to the definition point.