Asynchronous Clock Domain Crossings - Asynchronous Clock Domain Crossings - 2026.1 English - UG903

The Timing Constraints wizard analyzes clock domain crossing (CDC) path topology between asynchronous clocks and recommends clock groups or false path constraints when safe.

Asynchronous clocks have no known phase relationship, which often occurs when they do not share the same primary clock or lack a common period. Slack computation on asynchronous CDC paths is inaccurate and unreliable. Large skew between asynchronous clocks can significantly affect and prevent timing closure if any of the asynchronous CDC paths are timed.

Add timing exceptions on these paths, such as set_clock_groups, set_false_path, or set_max_delay -datapath_only, to either ignore timing analysis or to ignore clock skew and uncertainty. Also ensure the design includes proper CDC circuitry to prevent metastability.

In the Vivado Design Suite, the wizard identifies only flip-flop-based synchronizers for synchronous data and asynchronous reset. For an example of such synchronizers, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

The following figure shows shows tables of recommended and non-recommended constraints.

The columns in both tables display the following information:

Source Clock

This is the clock of the CDC paths start points identified by the wizard.

Destination Clock

This is the clock of the CDC paths endpoints identified by the wizard.

Constraint

This column shows either the dominant timing exception or the characteristics of the clock relationship when there is no exception.

• In the Recommended Constraints table, the wizard anticipates created constraints and displays the new constraint:
  • asynch (clock groups) when it is safe to ignore timing in both directions. In this case, a set_clock_groups constraint is created.
  • asynch (false path) when it is only safe to ignore paths in one direction. In this case, a set_false_path constraint is created.
• In the Non-recommended Constraints table, the wizard shows how CDC paths are timed before applying a clock group or false path exception:
  • Timed - No Common Primary Clock
  • Timed - No Common Period
  • MaxDelay DataPath when at least one path is covered by a set_max_delay -datapath_only constraint and all other paths are covered by false path constraints

Endpoints

The number of CDC path endpoints identified by the wizard.

Synchronized (with ASYNC_REG)

The number of endpoints properly synchronized, with the ASYNC_REG property set to true on all synchronizer flip-flops.

Synchronizer without ASYNC_REG

The number of synchronizers where at least one flip-flop does not have the ASYNC_REG property set to true.

Unknown

The number of CDC path endpoints where the wizard did not find a synchronizer.

Max Delay Datapath Only

The number of CDC path endpoints that are constrained with a set_max_delay -datapath_only constraint.

The table entries contain cross-probing links whenever applicable. When you click a number, the Paths tab lists the corresponding CDC paths. You can select one or more CDC paths and click Schematic (F4) to display their logic in the main Vivado IDE window.