Assigning a Fixed Location to an RPM - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

Optionally use an RLOC_ORIGIN or LOC constraint to place and fix the location of an RPM on the device. In the Vivado IDE, these properties fix the RPM origin, or the lower-left corner of the RPM. Each remaining cell in the RPM set is placed by using the relative location (RLOC) to offset from the origin.

Figure 1. RPM Placement by RLOC_ORIGIN

The following example shows a hierarchical RPM that is fixed using RLOC_ORIGIN. RLOC constraints are assigned to the RPM register cells to create a two-up-by-three-across placement pattern.

In Verilog:

(* RLOC = "X0Y0" *) FDC sr0... 
(* RLOC = "X1Y0" *) FDC sr1... 
(* RLOC = "X2Y0" *) FDC sr2... 
(* RLOC = "X0Y1" *) FDC sr3... 
(* RLOC = "X1Y1" *) FDC sr4... 
(* RLOC = "X2Y1" *) FDC sr5...

The RPM is instantiated into the design three times with an RLOC on each cell:

(* RLOC = "X0Y0" *) ffs u0...
(* RLOC = "X3Y2" *) ffs u1...
(* RLOC = "X6Y4" *) ffs u2...

Finally, an RLOC_ORIGIN of X74Y15 is assigned to cell u0 resulting in the placement shown in Figure 1. The highlights in the above figure are explained in the below table.

Table 1. Cell Highlighting
Cell Highlight Color
u0 yellow
u1 green
u2 red
Tip: Although RPMs control the relative placement of logic elements, they do not insure that specific routing resources are used to connect the logic from one implementation to the next.

For more information on controlling the routing used, see Routing Constraints.