Adjusting Constraints for Synthesis Logic Replication - Adjusting Constraints for Synthesis Logic Replication - 2026.1 English - UG903

During synthesis, Vivado can replicate registers to improve performance. Your XDC constraints do not automatically update to include replicated cells. If your timing constraint targets an object replicated by Vivado synthesis, the replicated cells might not be covered. depends on how you wrote the constraint. Missing coverage can reduce implementation quality.

Use the get_cells and get_pins commands to include replicated objects automatically.

For example, rewrite a false path so it safely includes replicated objects during implementation.

set_false_path -from [get_cells -hierarchical *rx_reg -include_replicated_objects]

Vivado sets the ORIG_CELL_NAME property on replicated objects. The -include_replicated_objects option relies on this property. The following queries return the original cells together with the replicated ones:

You can query both original and replicated cells with the following command:

get_cells -include_replicated_objects *rx_reg
get_cells -include_replicated_objects [get_cells -hier -filter {NAME =~ *rx_reg}] 
get_cells -hierarchical -filter {NAME =~ *rx_reg || ORIG_CELL_NAME =~ *rx_reg}

The -filter option runs after Vivado builds the object collection. Avoid using -filter with -include_replicated_objects if your filter tests NAME. Replicated objects with names that do not match the NAME pattern are excluded from the results.

For example, the following command excludes replicated objects matching *reg_replica*:

get_cells -include_replicated_objects -filter {NAME =~ *rx_reg}

AMD recommends that you run report_methodology to perform methodology checks. Review the XDCV-1 and XDCV-2 messages to find constraints that need updates. Update these constraints with the get_cells and get_pins options.

Figure 1. Creating Constraints with the Synthesized Design

Before starting implementation, verify that your design has no major timing violations. Place-and-route tools fix reasonable violations but not fundamental design issues. Fundamental issues prevent timing closure.

For more information on running timing analysis, refer to the Vivado Design Suite User Guide: Synthesis (UG901). For more information on Guiding Implementation with Design Constraints in the Vivado Design Suite User Guide: Implementation (UG904).