When you use OOC synthesis mode, OOC modules such as IP, BD, and DFx appear as black boxes at the top level. As a result, netlist objects inside these OOC modules are not accessible to top-level constraints. This requires the constraints used for synthesis to differ from those used for implementation.
In project mode you can create a specific XDC file for synthesis and set the
properties to USED_IN_SYNTHESIS=TRUE and USED_IN_IMPLEMENTATION=FALSE. For implementation, use a
separate top-level XDC with USED_IN_SYNTHESIS=FALSE.
In black‑box modules, only input and output ports are accessible. This limits the timing constraints the top level can specify for these modules. Top‑level constraint limitations in OOC synthesis include the following:
- Auto‑derived clocks inside an OOC module cannot be renamed.
- Clock names defined inside an OOC module cannot be referenced at the top level. The tool names the clock based on the net connected to the module port, not the internal name, even if renamed inside the module XDC.
get_clocks -of_objects [get_pins <MODULE_OOC_OUTPUT_CLOCK_PORT>]