Adjust Constraints for Synthesis with Black-Boxes - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

When using Out-Of-Context (OOC) synthesis mode, the OOC modules (IP/BD/DFx/…) are inferred as a black-box inside the top level. This means that the netlist objects inside the OOC modules are not accessible by the top-level constraints. This may require the top-level constraints for synthesis to be different from the constraints for implementation. In Project Mode, this can be done by creating a specific XDC file for synthesis and setting the properties USED_IN_SYNTHESIS=TRUE & USED_IN_IMPLEMENTATION=FALSE on it. The top-level XDC for implementation should have USED_IN_SYNTHESIS=FALSE.

The only objects accessible from the black-boxes are the input and output ports. This limits the type of timing constraints that the top-level can specify when referring to a black-box.

Some of the limitations for the top-level constraints from OOC synthesis are:

  • Auto-derived clocks generated inside the OOC module cannot be renamed.
  • Clock names defined inside the OOC module cannot be referred to. The clock propagating to the output of the OOC module is named based on the net connected to the port of the module. It is not from the name it has inside the module, even if the clock is renamed inside the module XDC.
  • If the top-level constraints need to refer to the clock coming out of an OOC module, it should use a query such as ‘get_clocks -of_objects [get_pins <MODULE_OOC_OUTPUT_CLOCK_PORT>]’.