Additional Clock Uncertainty - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

Use the set_clock_uncertainty command to define additional clock uncertainty for different corner, delay, or particular clock relationships as needed. This is a convenient way to add extra margin to a portion of the design from a timing perspective.

The inter-clock uncertainty always takes precedence over simple clock uncertainty, regardless of the order of the constraints. In the following example, although a simple clock uncertainty of 1.0 ns is defined last on clock clk1, the timing paths from clock clk1 to clock clk2 are constrained with a 2.0 ns clock uncertainty.

set_clock_uncertainty 2.0 -from [get_clocks clk1] -to [get_clocks clk2] set_clock_uncertainty 1.0 [get_clocks clk1]

When an inter-clock uncertainty is defined between two clock domains, make sure to constrain all the possible interactions of clock domains:

  • clk1 to clk2
  • clk2 to clk1