About Timing Exceptions - About Timing Exceptions - 2026.1 English

About Timing Exceptions - About Timing Exceptions - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID

UG903

Release Date

2026-07-01

Version

2026.1 English

A timing exception is needed when the logic behaves in a way that is not timed correctly by default. Use a timing exception command whenever you want the timing handled differently, for example when logic captures results every other clock cycle.

The AMD Vivado™ IDE supports the timing exceptions commands shown in the following table:

Table 1. Timing Exceptions Commands
Command	Function
`set_multicycle_path`	Indicates the number of clock cycles required to propagate data from the start to the end of a path.
`set_false_path`	Indicates that a logic path in the design is not be analyzed.
`set_max_delay` and `set_min_delay`	Sets the maximum and minimum delay values for a path, overriding the default setup and hold constraints with user-specified values.

Note: For runtime considerations, Vivado tools do not perform on the fly analysis for conflicting timing exceptions. Run report_exceptions for full analysis and reporting. For more information, refer to Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).