Generated clocks are driven inside the design by special cells called Clock Modifying
Blocks, such as an MMCM, or by user logic. Each generated clock is associated with a
master clock. The create_generated_clock command references the start
point of the master clock, which can be either a primary clock or another generated
clock.
Generated clocks inherit properties from their master clock. Rather than specifying the period or waveform directly, describe how the modifying logic transforms the master clock.
The relationship between a master clock and a generated clock can involve the following:
- A simple frequency division
- A simple frequency multiplication
- A combination of multiplication and division to achieve a non-integral ratio (commonly used with MMCM and PLL)
- A phase shift or a waveform inversion
- A duty cycle transformation
- A combination of all the above
Recommended: Define all primary clocks first, as
they are needed to define generated clocks.
Note: The tool computes generated clock latency
by tracing sequential and combinational paths between the generated clock source pin and
the master clock source pin. To limit this to only combinational paths, use the
combinational option.