About Generated Clocks - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

Generated clocks are driven inside the design by special cells called Clock Modifying Blocks (for example, an MMCM), or by some user logic.

Generated clocks are associated with a master clock. The create_generated_clock command considers the start point of the master clock. The master clock can be a primary clock or another generated clock.

Generated clock properties are directly derived from their master clock. Instead of specifying their period or waveform, you must describe how the modifying circuitry transforms the master clock.

The relationship between a master clock and a generated clock can be any of the following:

  • A simple frequency division
  • A simple frequency multiplication
  • A combination of a frequency multiplication and division in order to obtain a non-integral ratio (usually done by MMCM and PLL)
  • A phase shift or a waveform inversion
  • A duty cycle transformation
  • A combination of all the above
Note: To compute the latency for the generated clock, the tool traces both sequential and combinational paths between the source pin of the generated clock and the source pin of the master clock. In some cases, it might be desirable to only trace through combinational paths to calculate the generated clock latency. You can do this using the -combinational command line option.