Design constraints define the requirements that the compilation flow must meet for the design to function on the board. Not all constraints apply to every step in the compilation flow. For example, you use physical constraints only during implementation (that is by the placer and router).
Because the AMD Vivado™ Integrated Design Environment (IDE) synthesis and implementation algorithms are timing-driven, follow these guidelines:
- Create proper timing constraints that match your application requirements.
- Avoid over-constraining the design, which makes timing closure more difficult.
- Avoid under-constraining the design, which can prevent accurate timing analysis.
- Use reasonable constraints to improve the likelihood of meeting timing goals.