In your digital design, clocks provide the time reference to transfer data reliably from register to register. The AMD Vivado™ Integrated Design Environment (IDE) timing engine uses clock characteristics to compute timing path requirements and report timing margin through slack.
For more information, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
Define clocks properly to get maximum timing path coverage with the best accuracy. Define a clock with the following characteristics:
- Define it on the driver pin or port of its tree root (the source point).
- Describe its edges with the combination of the period and waveform properties.
- Specify the period in nanoseconds; it corresponds to the time over which the waveform repeats.
- Provide the waveform as the list of rising and falling edge absolute times, in nanoseconds, within the clock period. Use an even number of values. The first value corresponds to the first rising edge. Unless you specify otherwise, the duty cycle defaults to 50% and the phase shift to 0 ns.
The following figure shows two examples:
- Clk0 has a 10 ns period, 50% duty cycle, and 0 ns
phase.
Clk0: period = 10, waveform = {0 5} - Clk1 has an 8 ns period, 75% duty cycle, and 2 ns phase
shift.
Clk1: period = 8, waveform = {2 8}
Figure 1. Clock Waveforms Example
