By default, the Vivado IDE times paths between
all clocks in your design. You can change this by using clock groups or false path
constraints. set_clock_groups disables timing between
groups of clocks you identify, not within a group. Unlike set_false_path, timing is ignored in both directions between grouped
clocks.
Specify multiple groups by repeating the -group option. If no clocks in
a group exist, that group becomes empty. set_clock_groups remains valid
only when at least two groups are non-empty. If only one group remains and others are
empty, it is not applied. Vivado IDE generates an error in that case.
Use the schematic viewer or the clock networks report to visualize clock-tree topology. Determine which clocks you must not time together. You can also use the clock interactions report to review constraints between two clocks. Identify clocks sharing a primary clock or a known phase relationship. Also identify clocks with no common period, reported as unexpandable.