About Bus Skew Constraints - About Bus Skew Constraints - 2026.1 English - UG903

Use the bus skew constraint to set a maximum skew across several asynchronous CDC paths. The bus skew is not the traditional clock skew of a timing path. Instead, it equals the largest capture-time difference across all paths covered by one set_bus_skew constraint. The bus skew requirement applies to both Fast and Slow corners, but not across the corners.

The intent of the bus skew constraint is to limit how many source clock edges can launch a data captured by a single destination clock edge. The tolerance depends on the CDC synchronization scheme used for the constrained paths. The bus skew constraint is typically used for the following:

• Gray-coded bus transfer, such as in asynchronous FIFOs
• Multi-bit CDC implemented with CE, MUX, or MUX Hold circuitry
• Configuration registers

Do not add a bus skew constraint to a safely timed synchronous CDC; it is unnecessary. Setup and hold checks already guarantee a safe transfer between those paths.

The CDC scenarios for bus skew constraints are as follows:

• Asynchronous CDC covered with set_clock_groups
• Asynchronous CDC entirely covered with set_false_path and/or set_max_delay -datapath_only
• Synchronous CDC paths covered with set_false_path and/or set_max_delay -datapath_only

Treat the bus skew constraint as a timing assertion, not a timing exception. It does not interfere with timing exceptions (set_clock_groups, set_false_path, set_max_delay, set_max_delay -datapath_only, set_multicycle_path) or their precedence.

The bus skew constraint is only optimized by the route_design command. Report them with report_bus_skew at the Tcl Console, or use Reports > Timing > Report Bus Skew in the AMD Vivado™ IDE. The Timing Summary report (report_timing_summary) does not include bus skew constraints.