Verilog Wire Example - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English
(* dont_touch = "yes" *) wire sig1;
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;
(* dont_touch="true" *) input data;
Note: A port declaration implicitly declares a wire with the same name as the port. You can apply dont_touch as an attribute on module ports.