Verilog Syntax - Verilog Syntax - 2026.1 English

Verilog Syntax - Verilog Syntax - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

To set this attribute, place the proper Verilog attribute syntax on the signal in question:

(* MARK_DEBUG = "{TRUE|FALSE}" *)