Verilog Syntax Example - Verilog Syntax Example - 2026.1 English

Verilog Syntax Example - Verilog Syntax Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

// Marks an internal wire for debug
(* MARK_DEBUG = "TRUE" *) wire debug_wire,