Verilog Reserved Keywords - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

The following table lists the reserved keywords. Keywords marked with an asterisk (*) are reserved by Verilog and are not supported by Vivado synthesis.

Table 1. Verilog Reserved Keywords
always and assign automatic
begin buf bufif0 bufif1
case casex casez cell*
cmos* config* deassign default
defparam design* disable edge
else end endcase endconfig*
endfunction endgenerate endmodule endprimitive
endspecify endtable endtask event
for force forever fork
function generate genvar highz0
highz1 if ifnone incdir*
include* initial inout input
instance* integer join larger
liblist* library* localparam macromodule
medium module nand negedge
nmos* nor noshow-cancelled* not
notif0 notif1 or output
parameter pmos* posedge primitive
pull0 pull1 pullup* pulldown*
pulsestyle_ondetect* pulsestyle_onevent* rcmos* real
realtime reg release repeat
rnmos* rpmos* rtran* rtranif0*
rtranif1* scalared show-cancelled* signed
small specify specpa strong0
strong1 supply0 supply1 table
task time tran* tranif0*
tranif1* tri tri0 tri1
triand trior trireg use*
vectored wait wand weak0
weak1 while wire wor
xnor xor