Verilog Module Example - Verilog Module Example - 2026.1 English

Verilog Module Example - Verilog Module Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

(* DONT_TOUCH = "yes" *)
module example_dt_ver
(clk,
In1,
In2,
out1);