Verilog Instance Example - 2025.1 English - UG901
Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2025-06-11
Version
2025.1 English
(* DONT_TOUCH = "yes" *) example_dt_ver U0 (.clk(clk), .in1(a), .in2(b), out1(c));