Verilog Design - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

Often, a top-down methodology is used to design complex circuits.

  • At each stage of design process, different design specifications are needed. For example, at the architectural level, a specification can correspond to a block diagram or an Algorithmic State Machine (ASM) chart.
  • A block or ASM stage corresponds to a register transfer block in which the connections are N-bit wires, such as:
    • Register
    • Adder
    • Counter
    • Multiplexer
    • Interconnect logic
    • Finite State Machine (FSM)
  • Verilog allows the expression of notations such as ASM charts and circuit diagrams in a computer language.