VHDL and Verilog Boundary Rules - VHDL and Verilog Boundary Rules - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID: UG901
Release Date: 2026-07-08
Version: 2026.1 English

VHDL and Verilog boundary rules are, as follows:

The boundary between VHDL and Verilog is enforced at the design unit level.
A VHDL entity or architecture can instantiate a Verilog module. See Instantiating VHDL in Verilog in the following section.
A Verilog module can instantiate a VHDL entity. See Instantiating Verilog in VHDL.