VHDL Sequential Processes Without a Sensitivity List - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

Vivado synthesis allows the description of a sequential process using a wait statement. The sequential process is described without a sensitivity list.

The wait statement is the first statement and the condition in the wait statement describes the sequential logic clock.

Important: You cannot have both, a sensitivity list and a wait statement, for the same sequential process. Only one wait statement is allowed for the sequential process.