VHDL GENERICS - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

VHDL GENERICs have the following properties:

  • Are equivalent to Verilog parameters.
  • Help you create scalable design modelizations.
  • Let you write compact, factorized VHDL code.
  • Let you parameterize functionality such as bus size, and the number of repetitive elements in the design unit.

To instantiate the same functionality with different bus sizes, describe one generic design unit. See the GENERIC Parameters Example.