VHDL Entity Declarations - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

Declare the I/O ports of the circuit in the entity. Each port has a:

  • name
  • mode (in, out, inout, buffer)
  • type