VHDL Component Instantiation - 2025.2 English - UG901

Component instantiation allows you to instantiate one design unit (component) inside another design unit to create a hierarchically structured design description.

To perform component instantiation:

1. Create the design unit (entity and architecture) modeling the functionality to be instantiated.
2. In the parent design unit's architecture, declare the component in the declarative region so you can instantiate it.
3. Instantiate and connect this component in the architecture body of the parent design unit.
4. Map (connect) formal ports of the component to actual signals and ports of the parent design unit.