VHDL Assert Statements - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

With the -assert synthesis option, assert statements are supported.

CAUTION:
Be careful while using asserts. Vivado can only support static asserts that do not create or are created by behavior. For example, performing as assert on a value of a constant or an operator/generic works. However, as an asset on the value of a signal inside an if statement does not work.