In VHDL, when you list items in a process's sensitivity list for combinational logic, you must include every signal the process reads. The designer bears responsibility for ensuring the sensitivity list is complete. If any were missed, there would be Warning messages and possible latches inferred in the design.
With VHDL-2008, you can use the process(all) statement that looks for all the inputs to the process and
creates the logic.
process(all) begin
enable <= en1 and en2;
end process;