You can set some synthesis attributes from an XDC file as well as the original RTL file. In general, attributes that are used in the end stages of synthesis and describe how synthesis- created logic is allowed in the XDC file. The XDC does not allow attributes that the compiler uses at the start of synthesis.
For example, the XDC does not allow the KEEP and
DONT_TOUCH attributes.
When the tool reads attributes from the XDC file, it has already
optimized components marked KEEP or DONT_TOUCH. Those
components therefore no longer exist when the tool reads the attribute. For that reason,
those attributes must always be set in the RTL code. For more information on where to
set specific attributes, see the individual attribute descriptions in this chapter.
To specify synthesis attributes in XDC, type the following in the Tcl Console:
set_property <attribute> <value> <target>For example:
set_property MAX_FANOUT 15 [get_cells in1_int_reg]In addition, you can set these attributes in the elaborated design, as follows:
- Open the elaborated design, then select the item where you want to place an
attribute using one of the following methods:
- Click the item in the schematic.
- Select the item in the RTL
Netlist view, as shown in the following
figure.
- In the Cell Properties window, click
the Properties tab, and do one of the
following:
- Modify the property.
- If the property does not exist, right-click, select Add Properties, and select the property from the window that appears, or click the + sign.
This saves the attributes to your current constraint file or creates a new constraint file if one does not exist.