Unsupported Verilog Gate Level Primitives - Unsupported Verilog Gate Level Primitives - 2026.1 English

Unsupported Verilog Gate Level Primitives - Unsupported Verilog Gate Level Primitives - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

The table lists the gate-level primitives not supported in Vivado synthesis.