Unsupported Verilog Gate Level Primitives - 2025.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2025-12-05
Version
2025.2 English

The table lists the gate-level primitives not supported in Vivado synthesis.

Table 1. Unsupported Primitives
Primitive Status
pulldown and pullup Unsupported
drive strength and delay Ignored
Arrays of primitives Unsupported