Previously, in VHDL, types and subtypes had to be fully constrained in declaring the type. In VHDL-2008, it is allowed to be unconstrained, and the constraining happens with the objects that are of that type; consequently, types and subtypes are more versatile. For example:
subtype my_type is std_logic_vector;
signal my_reg1 : my_type (3 downto 0);
signal my_reg2 : my_type (4 downto 0);
In previous VHDL versions, the example was done by 2 subtypes. You can accomplish this in one type in VHDL-2008. Arrays are processed similarly, as shown in this example:
type my_type is array (natural range <>) of std_logic_vector;
signal : mytype(1 downto 0)(9 downto 0);