Read each attribute to decide if it belongs on hierarchies or signals.
In general, placing an attribute on a hierarchy affects only its
boundary, not items inside it. For example, placing a DONT_TOUCH on a specific level affects that level only, and not the
signals inside that level.
There are some exceptions to this rule. These are DSP_FOLDING , RAM_STYLE,
ROM_STYLE, SHREG_EXTRACT, and USE_DSP. When you
place attributes on a hierarchy, they also affect the signals inside it.
Note: For the Verilog syntax of having the attribute inside
block comments, /* attr = value */, this attribute is attached to the next lexical item
after the comment. If the comment is on its own line, the next item in the RTL, no
matter how far down, gets the attribute. Specifying the attribute at the end of the file
attaches it to the module.