Supported Constructs in Vivado - Supported Constructs in Vivado - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2026-07-08
Version
2026.1 English

Conditional expressions are supported in the following contexts:

  1. General Expression
  2. Initializers for constants, signals, and variables
  3. Attribute specifications
  4. Generic map, port map (interface association list)
  5. In Function return statements
  6. Conditional or Unaffected expression

Examples:

General Expression:
out1 <= (in1 xor C when C1 = '0' else in1 and C) when in1 > C else
(in1 or C when C1 = '0' else in1 or C);
Initializers for constants, signals, and variables:
constant C: std_logic_vector(3 downto 0) := "1101" when C1 = '0' else"1000";
out1 <= (in1 xor C when C1 = '0' else in1 and C) when in1 > C else
(in1 or C when C1 = '0' else in1 or C);
Attribute specifications:
attribute USE_DSP48 of p1 : signal is "yes" when dsp = 1 else "no";
Interface association list:
entity bot is
generic (C1: std_logic := '0');
port(in1: in std_logic_vector(3 downto 0);
out1: out std_logic_vector(3 downto 0));
end entity bot;
u0: bot generic map(C1 => C1) port map (in1 => in1 when C1 = '1' else in2,out1 => out1);
In Function return statements:
function Mux4_3 (
Sel : std_logic_vector(1 downto 0);
A, B, C, D : std_logic_vector
) return std_logic_vector is
begin
return Mux4(Sel, A, B, C, D) when C1 = 1 else Mux4_2(Sel, A, B, C, D) ;
end function Mux4_3 ;
Unaffected expression:
package body MuxPkg is
function Mux4 (
Sel : std_logic_vector(1 downto 0);
A, B, C, D : std_logic_vector
) return std_logic_vector is
begin
return A when Sel = "00" else unaffected ;
return B when Sel = "01" else unaffected ;
return C when Sel = "10" else unaffected ;
return D when Sel = "11" else unaffected ;
return (A'range => 'X') ;
end function Mux4 ;
end package body MuxPkg ;