Vivado synthesis supports VHDL-2019 subtype inference in two related areas:
- Infer subtype from initial
value:Example:
entity top is port(in1,in2 : in unsigned(3 downto 0); out1 : out unsigned(3 downto 0)); end entity top; architecture beh of top is signal s: unsigned := in1+in2; begin out1 <= s; end architecture; - Function return subtype inferred from
context:Example:
function get_len(b : boolean) return r of unsigned is begin --return to_unsigned(5, 5); -- this is ok -- when b else to_unsigned(6, 6); -- Conditional assignments forreturns not supported -- the following are not ok -- return r; return to_unsigned(r'length, r'length); end function; signal s1:unsigned(3 downto 0); begin s1 <= get_len(true);