Setting Synthesis Inputs - 2025.2 English - UG901

Vivado synthesis allows two input types: RTL source code and timing constraints. To add RTL or constraint files to the run:

1. From the File menu or the Flow Navigator, select the Add Sources command to open the Add Sources wizard, shown in the following figure.
   
   
2. Select an option corresponding to the files to add, and click Next.
   If Add or Create Design sources is selected, the following figure shows the Add or Create Design Sources page.
   
   
3. Add constraint, RTL, or other project files, click Finish.

   See Vivado Design Suite User Guide: System-Level Design Entry (UG895) for more information about creating RTL source projects.

   The Vivado synthesis tool reads files in VHDL, Verilog, SystemVerilog, or mixed language options.

   The following chapters provide details on supported HDL constructs.

   • HDL Coding Techniques
   • VHDL Support
   • VHDL-2008 Language Support
   • Verilog Language Support
   • SystemVerilog Support
   • Mixed Language Support

   Vivado synthesis also supports several RTL attributes that control synthesis behavior. Synthesis Attributes describes these attributes. For timing constraints, Vivado synthesis uses the XDC file.

   Using Block Synthesis Strategies describes the available Block Synthesis Strategies.

   Important: Vivado Design Suite does not support the UCF format. See ISE to Vivado Design Suite Migration Guide (UG911) for the UCF to XDC conversion procedure.