SHREG_EXTRACT VHDL Example - SHREG_EXTRACT VHDL Example - 2026.1 English

SHREG_EXTRACT VHDL Example - SHREG_EXTRACT VHDL Example - 2026.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2026-07-08

Version

2026.1 English

attribute shreg_extract : string;
attribute shreg_extract of my_srl : signal is "no";