The Tcl command to run synthesis is synth_design.
Typically, this command is run with multiple options, for example:
synth_design -part xc7k30tfbg484-2 -top my_topIn this example, synth_design is run with the
-part option and the -top
option.
In the Tcl Console, you can set synthesis options and run synthesis using Tcl
command options. To retrieve a list of options, type synth_design
-help in the Tcl Console. The following snippet is an example of the -help output: synth_design -help.
Description: Synthesize a design using
Vivado Synthesis and open that
design
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Syntax: synth_design
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[-name <arg>] [-part <arg>] [-constrset <arg>]
[-top <arg>]
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[-include_dirs <args>] [-generic <args>]
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[-verilog_define <args>]
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[-flatten_hierarchy <arg>]
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[-gated_clock_conversion <arg>]
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[-directive <arg>] [-rtl] [-bufg <arg>]
[-no_lc]
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[-shreg_min_size <arg>] [-mode <arg>]
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[-fsm_extraction
<arg>][-rtl_skip_mlo][-rtl_skip_ip]
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[-rtl_skip_constraints]
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[-keep_equivalent_registers] [-resource_sharing
<arg>]
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[-cascade_dsp <arg>] [-control_set_opt_threshold
<arg>]
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[-max_bram <arg>] [-max_uram <arg>]
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[-max_dsp <arg>] [-max_bram_cascade_height
<arg>]
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[-max_uram_cascade_height <arg>]
[-global_retiming]
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[-no_srlextract]
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[-assert] [-no_timing_driven] [-sfcu] [-debug_log]
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[-quiet] [-verbose]
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Returns:
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Usage:
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Name
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Description
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[-name]
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Design name
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[-part]
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Target part
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[-constrset]
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Constraint fileset to use
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[-top]
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Specify the top module name.
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[-include_dirs]
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Specify verilog search directories.
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[-generic]
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Specify generic parameters. Syntax: -generic <name>=<value> -generic
<name>=<value> ...
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[-verilog_define]
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Specify verilog defines. Syntax: -verilog_define <macro_name>[=<macro_text>]
-verilog_define <macro_name>[=<macro_text>]
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[-flatten_hierarchy]
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Flatten hierarchy during LUT mapping. Values: zull, none, rebuilt. Default: rebuilt
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[-gated_clock_conversion]
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Convert clock gating logic to flop enable.Values: off, on, auto Default: off
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[-directive]
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Synthesis directive. Values: default, RuntimeOptimized, AreaOptimized_high,
AreaOptimized_medium, AlternateRoutability, AreaMapLargeShiftRegToBRAM, AreaMultThresholdDSP,
FewerCarryChains. Default: default
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[-rtl]
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Elaborate and open an rtl design.
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[-bufg]
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Max number of global clock buffers used by synthesis. Default = 12
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[-no_lc]
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Disable LUT combining. Do not allow combining.
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[-shreg_min_size]
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Minimum length for chain of registers to be mapped onto SRL. Default: 3
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[-mode]
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The design mode. Values: default, out_of_context. Default: default
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[-fsm_extraction]
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FSM Extraction Encoding. Values: off, one_hot, sequential, johnson, gray, user_encoding,
auto. Default: auto
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[-rtl_skip_mlo]
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Skip mandatory logic optimization for RTL elaboration of the design; requires -rtl
option.
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[-rtl_skip_ip]
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Exclude subdesign checkpoints in the RTL elaboration of the design; requires -rtl
option.
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[-rtl_skip_constraints]
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Do not load and validate constraints against elaborated design; requires -rtl option.
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[-srl_style]
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Static SRL Implementation Style. Values: register, rl, srl_reg, reg_srl, reg_srl_reg.
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[-keep_equivalent_registers]
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Prevents registers sourced by the same logic from being merged. (Note that the merging can
otherwise be prevented using the synthesis KEEP attribute).
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[-resource_sharing]
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Sharing arithmetic operators. Value: auto, on, off. Default: auto
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[-cascade_dsp]
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Controls how adders summing DSP block outputs will be implemented. Value: auto, tree, force.
Default: auto
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[-control_set_opt_threshold]
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Threshold for synchronous control set optimization to lower number of control sets. Valid
values are 'auto' and non-negative integers. The higher the number, the more control set
optimization will be performed and fewer control sets will result. To disable control set
optimization completely, set to 0. Default: auto
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[-max_bram]
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Maximum number of block RAM allowed in design. (Note -1 means that the tool will choose the
max number allowed for the part in question). Default: -1
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[-max_uram]
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Maximum number of UltraRAM blocks allowed in design. (Note -1 means that the tool will choose
the max number allowed for the part in question). Default: -1
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[-max_dsp]
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Maximum number of block DSP allowed in design. (Note -1 means that the tool will choose the
max number allowed for the part in question). Default: -1
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[-max_bram_cascade_height]
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Controls the maximum number of BRAM that can be cascaded by the tool. (Note -1 means that the
tool will choose the max number allowed for the part in question). Default: -1
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[-max_uram_cascade_height]
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Controls the maximum number of UtraRAM that can be cascaded by the tool. (Note -1 means that
the tool will choose the max number allowed for the part in question). Default:1
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[-global_retiming]
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Seeks to improve circuit performance for intra-clock sequential paths by automatically moving
registers (register balancing) across combinatorial gates or LUTs.It maintains the original behavior
and latency of the circuit and does not require changes to the RTL sources. A value of "on" turns on
retiming, "off" turns off retiming and "auto" will allow the tool to decide. "auto" will have
retiming turns on for Versal devices and off for non-Versal devices.
Default: "auto"
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[-no_srlextract]
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Prevents the extraction of shift registers so that they get implemented as simple
registers.
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[-assert]
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Enable VHDL assert statements to be evaluated. A severity level of failure will stop the
synthesis flow and produce an error.
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[-no_timing_driven]
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Do not run in timing driven mode.
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[-sfcu]
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Run in single-file compilation unit mode.
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[-debug_log]
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Print detailed log files for debugging.
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[-quiet]
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Ignore command errors.
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[-verbose]
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Suspend message limits during command
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For the -generic option, special handling needs
to happen with VHDL boolean and std_logic_vector types because
those type do not exist in other formats. Instead of TRUE, FALSE, or 0010, for example, Verilog
standards should be given.
For boolean, the value for FALSE is:
-generic my_gen=1‘b0For std_logic_vector, the value for 0010 is:
-generic my_gen=4‘b0010Note: Overriding string generics or parameters is not
supported.
Note: If you are using the
-mode
out_of_context option on the top-level, do not use the PACKAGE_PIN property unless there is
an I/O buffer instantiated in the RTL. The out_of_context option
tells the tool to not infer any I/O buffers including tristate buffers. Without the buffer, you get
errors in placer.A verbose version of the help is available in the Vivado Design Suite Tcl Command Reference Guide (UG835). To determine any Tcl equivalent to a Vivado IDE action, run the command in the Vivado IDE and review the content in the Tcl Console or the log file.